module cond_carry_adder_4bit(
  a0,b0,a1,b1,a2,b2,a3,b3,
  c0,c1,c2,c3,s0,s1,s2,s3);

  input    a0,a1,a2,a3;
  input    b0,b1,b2,b3;
  output   c0,c1,c2,c3;
  output   s0,s1,s2,s3;

  wire c10, c11, c20, c21, c30, c31;
  wire c311,c301;
  
  assign s0   = a0 ^ b0;
  assign c0   = a0 & b0;
  
  assign s1   = a1 ^ b1 ^ c0;
  assign c10  = a1 & b1;
  assign c11  = a1 | b1;
  assign c1   = c0 ? c11 : c10;

  assign s2   = a2 ^ b2 ^ c1;
  assign c20  = a2 & b2;
  assign c21  = a2 | b2;
  assign c2   = c1 ? c21 : c20;

  assign s3   = a3 ^ b3 ^ c2;
  assign c30  = a3 & b3;
  assign c31  = a3 | b3;
  assign c311 = c21 ? c31 : c30;
  assign c301 = c20 ? c31 : c30;
  assign c3   = c1  ? c311 : c301;


endmodule
