module cond_carry_adder(
   a0,b0,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7,
   s0,s1,s2,s3,s4,s5,s6,c7,s7);//,final_sum);

  input  a0,a1,a2,a3,a4,a5,a6,a7;
  input  b0,b1,b2,b3,b4,b5,b6,b7;
  output c7;
  output s0,s1,s2,s3,s4,s5,s6,s7;
  //output [8:0] final_sum;

  wire c0,c1,c2,c3,c4,c5,c6;
  wire c10, c11, c20, c21, c30, c31, c40, c41, c50, c51, c60, c61, c70, c71;
  wire c311,c301,c511,c501,c611, c601, c711, c701, c712, c702;

  assign s0   = a0 ^ b0;
  assign c0   = a0 & b0;
  
  assign s1   = a1 ^ b1 ^ c0;
  assign c10  = a1 & b1;
  assign c11  = a1 | b1;
  assign c1   = c0 ? c11 : c10;

  assign s2   = a2 ^ b2 ^ c1;
  assign c20  = a2 & b2;
  assign c21  = a2 | b2;
  assign c2   = c1 ? c21 : c20;

  assign s3   = a3 ^ b3 ^ c2;
  assign c30  = a3 & b3;
  assign c31  = a3 | b3;
  assign c311 = c21 ? c31 : c30;
  assign c301 = c20 ? c31 : c30;
  assign c3   = c1  ? c311 : c301;

  assign s4   = a4 ^ b4 ^ c3;
  assign c40  = a4 & b4;
  assign c41  = a4 | b4;
  assign c4   = c3 ? c41 : c40;

  assign s5   = a5 ^ b5 ^ c4;
  assign c50  = a5 & b5;
  assign c51  = a5 | b5;
  assign c511 = c41 ? c51 : c50;
  assign c501 = c40 ? c51 : c50;
  assign c5   = c3  ? c511 : c501;

  assign s6   = a6 ^ b6 ^ c5;
  assign c60  = a6 & b6;
  assign c61  = a6 | b6;
  assign c611 = c511 ? c61 : c60;
  assign c601 = c501 ? c61 : c60;
  assign c6   = c3   ? c611 :c601;

  assign s7   = a7 ^ b7 ^ c6;
  assign c70  = a7 & b7;
  assign c71  = a7 | b7; 
  assign c711 = c61  ? c71 : c70;
  assign c701 = c60  ? c71 : c70;
  assign c712 = c511 ? c711 : c701; 
  assign c702 = c501 ? c711 : c701;
  assign c7   = c3   ? c712 : c702;

  //assign final_sum[0] = s0;
  //assign final_sum[1] = c0 ^ s1;
  //assign final_sum[2] = c1 ^ s2;
  //assign final_sum[3] = c2 ^ s3;
  //assign final_sum[4] = c3 ^ s4;
  //assign final_sum[5] = c4 ^ s5;
  //assign final_sum[6] = c5 ^ s6;
  //assign final_sum[7] = c6 ^ s7;
  //assign final_sum[8] = c7;
  
endmodule
