# Each gate will have following additional variants as well 
# One with better delay values and other with better no of transistors thereby leading to better area number 
# The other variation would be functions with different algebraic expressions but similar boolean meaning. 
# Gates with TIGFETs is assumed to occupy 1.25 times the area of RFET.
# Gates with MIGFETs is assumed to occupy 1.5 times the area of RFET. 

GATE inv1 1 O=!a; PIN * INV 1 999 1 0 1 0
GATE nand2_nor2_min3 sinw 3 2.625 O1=((!(a*b)) * !c) + ((!(a+b)) * c), O2 = !(a*b) , O3 = !(a+b) ; PIN * INV 1 999 1 0 1 0  
GATE xor2_xnor2_xor3f sinw super 3 5.5  O1=((a^b) * !p) + (!(a^b) * p),O2=a ^ b,O3 = !(a ^ b);  PIN * UNKNOWN 2 999 1 0 1 0  
GATE mux 4.5 O=(!s*a)+(b*s); PIN * NONINV 1 999 1 0 1 0 # this is an exception because only
GATE aoi_oai21 sinw 2 4 O1=!(a*b+c) , O2=!((a+b)*c); PIN * INV 1 999 1 0 1 0
GATE emux 8.5 O=((!(a*c + (!c)*b))*e) + (!(a*d + (!d)*b)*(!e));  PIN * NONINV 1 999 1 0 1 0
GATE nand3_nor3 sinw 2 3.25 O1= !(a*b*c), O2 = !(a+b+c); PIN * INV 1 999 1 0 1 0 
GATE zero	0	O=CONST0;
GATE buf 2 O=a; PIN * NONINV 1 999 1.0 0.0 1.0 0.0
GATE one	0	O=CONST1;
GATE maj_min sinw 2 4.75 O1= ((a*b)+(b*c)+(c*a)), O2=!((a*b)+(b*c)+(c*a)); PIN * NONINV 1 999 1 0 1 0 
GATE xor3_xnor3 sinw super 2 9.75  O1=(a^b^c), O2 = !(a^b^c); PIN * NONINV 1 999 1 0 1 0 


#GATE nand2_nor2_min3 sinw 2 1.625 O1 = !(a*b) , O2 = !(a+b) ; PIN * INV 1 999 1 0 1 0  
