.model cond_carry_adder_4bit
.inputs top^a0 top^a1 top^a2 top^a3 top^b0 top^b1 top^b2 top^b3
.outputs top^c0 top^c1 top^c2 top^c3 top^s0 top^s1 top^s2 top^s3

.names gnd
.names unconn
.names vcc
1

.names top^a0 top^b0 top^BITWISE_XOR~0^LOGICAL_XOR~40
01 1
10 1

.names top^a0 top^b0 top^BITWISE_AND~2^LOGICAL_AND~47
11 1

.names top^BITWISE_XOR~4^LOGICAL_XOR~48 top^BITWISE_AND~2^LOGICAL_AND~47 top^BITWISE_XOR~5^LOGICAL_XOR~41
01 1
10 1

.names top^BITWISE_AND~2^LOGICAL_AND~47 top^MULTI_PORT_MUX~11^LOGICAL_NOT~12 top^BITWISE_OR~9^LOGICAL_OR~50 top^BITWISE_AND~7^LOGICAL_AND~49 top^MULTI_PORT_MUX~11^MUX_2~46
1-1- 1
-1-1 1

.names top^BITWISE_XOR~14^LOGICAL_XOR~51 top^MULTI_PORT_MUX~11^MUX_2~46 top^BITWISE_XOR~15^LOGICAL_XOR~42
01 1
10 1

.names top^MULTI_PORT_MUX~11^MUX_2~46 top^MULTI_PORT_MUX~21^LOGICAL_NOT~22 top^BITWISE_OR~19^LOGICAL_OR~55 top^BITWISE_AND~17^LOGICAL_AND~53 top^MULTI_PORT_MUX~21^MUX_2~44
1-1- 1
-1-1 1

.names top^BITWISE_XOR~24^LOGICAL_XOR~56 top^MULTI_PORT_MUX~21^MUX_2~44 top^BITWISE_XOR~25^LOGICAL_XOR~43
01 1
10 1

.names top^MULTI_PORT_MUX~11^MUX_2~46 top^MULTI_PORT_MUX~21^LOGICAL_NOT~22
0 1

.names top^MULTI_PORT_MUX~11^MUX_2~46 top^MULTI_PORT_MUX~37^LOGICAL_NOT~38 top^MULTI_PORT_MUX~31^MUX_2~54 top^MULTI_PORT_MUX~34^MUX_2~52 top^MULTI_PORT_MUX~37^MUX_2~45
1-1- 1
-1-1 1

.names top^MULTI_PORT_MUX~11^MUX_2~46 top^MULTI_PORT_MUX~37^LOGICAL_NOT~38
0 1

.names top^BITWISE_AND~2^LOGICAL_AND~47 top^MULTI_PORT_MUX~11^LOGICAL_NOT~12
0 1

.names top^a1 top^b1 top^BITWISE_XOR~4^LOGICAL_XOR~48
01 1
10 1

.names top^a1 top^b1 top^BITWISE_AND~7^LOGICAL_AND~49
11 1

.names top^a1 top^b1 top^BITWISE_OR~9^LOGICAL_OR~50
1- 1
-1 1

.names top^a2 top^b2 top^BITWISE_XOR~14^LOGICAL_XOR~51
01 1
10 1

.names top^a2 top^b2 top^BITWISE_AND~17^LOGICAL_AND~53
11 1

.names top^BITWISE_AND~17^LOGICAL_AND~53 top^MULTI_PORT_MUX~34^LOGICAL_NOT~35 top^BITWISE_OR~29^LOGICAL_OR~58 top^BITWISE_AND~27^LOGICAL_AND~57 top^MULTI_PORT_MUX~34^MUX_2~52
1-1- 1
-1-1 1

.names top^BITWISE_AND~17^LOGICAL_AND~53 top^MULTI_PORT_MUX~34^LOGICAL_NOT~35
0 1

.names top^a2 top^b2 top^BITWISE_OR~19^LOGICAL_OR~55
1- 1
-1 1

.names top^BITWISE_OR~19^LOGICAL_OR~55 top^MULTI_PORT_MUX~31^LOGICAL_NOT~32 top^BITWISE_OR~29^LOGICAL_OR~58 top^BITWISE_AND~27^LOGICAL_AND~57 top^MULTI_PORT_MUX~31^MUX_2~54
1-1- 1
-1-1 1

.names top^BITWISE_OR~19^LOGICAL_OR~55 top^MULTI_PORT_MUX~31^LOGICAL_NOT~32
0 1

.names top^a3 top^b3 top^BITWISE_XOR~24^LOGICAL_XOR~56
01 1
10 1

.names top^a3 top^b3 top^BITWISE_AND~27^LOGICAL_AND~57
11 1

.names top^a3 top^b3 top^BITWISE_OR~29^LOGICAL_OR~58
1- 1
-1 1

.names top^BITWISE_AND~2^LOGICAL_AND~47 top^c0
1 1

.names top^MULTI_PORT_MUX~11^MUX_2~46 top^c1
1 1

.names top^MULTI_PORT_MUX~21^MUX_2~44 top^c2
1 1

.names top^MULTI_PORT_MUX~37^MUX_2~45 top^c3
1 1

.names top^BITWISE_XOR~0^LOGICAL_XOR~40 top^s0
1 1

.names top^BITWISE_XOR~5^LOGICAL_XOR~41 top^s1
1 1

.names top^BITWISE_XOR~15^LOGICAL_XOR~42 top^s2
1 1

.names top^BITWISE_XOR~25^LOGICAL_XOR~43 top^s3
1 1

.end

