B01

ECM-Type Devices as 3D Programmable Interconnects
(J. Knoch, I. Valov)

For creating the maximum benefit out of having active devices in the BEOL we need the possibility to re-wire the circuits on demand. While this can be done using transistors, a direct reconfigurable wiring scheme would be much more efficient. To this end we will build on the longstanding experience of the group at Forschungszentrum Jülich (FZJ) with electrochemical metallization resistive switching cells which provide many possibilities for the implementation of filamentary interconnects between two metallic electrodes. Based on this experience a new and flexible programmable routing scheme has been proposed that will be another flexible option to reconfigure circuits that can be used on the system level. The aim of during Phase 1 is to demonstrate the feasibility of such a flexible and programmable wiring approach based on the directional growth of filamentary interconnects.

B02

1T1R – 2D-FET and VCM-Device BEOL Integration
(S. Hoffmann-Eifert, Z. Wang)

One of the key features that make the approach of the active-3D very rewarding is the fact that switching devices and memory devices can be placed in close vicinity. The role of this project is to evaluate the potential of full-BEOL 1T1R elements realized by co-integration of a 2D-FET and a VCM device. In this sense, B02 already demonstrates the BEOL combination of two new elements as a starting point for further phases of the TRR. Moreover, this basic element allows to realize energy-efficient matrix-vector-multiplication on crossbar-arrays of 1T1R elements exploiting Kirchhoff’s laws.

B03

Reliability Assessment
(B. Max)

When bringing new electronic devices – both logic and memory – into practical systems, reliability is often the limiting factor. In this TRR we expect new reliability effects to show up since we use BEOL compatible materials and processes that have inherent higher defect density as well as novel device architectures. The role of this project is to assess the reliability on the device level already in an early phase, give feedback to the projects of Research Area A for required improvements on the device level and build a database that can be used in Phase 2 and 3 to establish tailored fault and degradation models and tolerance strategies to overcome the identified reliability issues.

B04

B04: Analog Computing Circuits Exploiting Devices Integrated into the BEOL
(R. Negra)

In a real life system analog design components are as important as digital building blocks. Moreover, for some functions energy consumption can be reduced by using an analog rather than a digital solution. However, the design of analog circuits is much more demanding since, in contrast to digital circuits, there is no inherent mechanism to avoid the propagation of errors. Therefore, special attention needs to be put towards constructing analog building blocks that make use of the new features offered by the BEOL integrated devices but also considers their shortcomings. In the first phase example circuits will be created that utilize of one or two of the BEOL integrated devices. Again, established devices will be used as the starting point in Phase 1.

B05

B05: Joint Logic, Memory, and Routing Synthesis
(A. Kumar, T. Gemmeke)

To assess morecomplex circuit and system options, an automated design environment is inevitable. Therefore, the central role of this project is to develop and maintain a simplified electronic design automation environment that will allow to design more complex systems in later phases. This is a crucial task since Active-3D eliminates boundaries between supply voltage and signals, memory, and logic and so forth, and therefore, new automated design strategies will be required and will need significant research and a continuous interaction with all other projects.

B06

B06: System Models, Architectures, and Application Mapping Tools
(J. Castrillon, R. Leupers)

The Active-3D approach will enable greatly enhanced possibilities for realizing complex systems. We
will not only see the enabling of new functionalities, but in Phases 1 and 2 we may have several architectural options to choose from. The mapping of the potential applications into system architectures is the central role of this project which will also supply valuable information for the selection of the device sets for future Phases 2 and 3.

B07

B07: Reconfigurable Architecture
(D. Göhringer, T. Gemmeke)

The possibility to reconfigure functionalities at runtime is a very good option to further improve the performance, flexibility and circuit complexity without increasing the device count. While A05 explores device level reconfigurability and B01 explores flexible wiring this project will specifically enable a portfolio of new reconfiguration schemes. Not only will we see new functionalities such as flexible and programmable routing but we will also be able to reconfigure circuits in three rather than two dimensions. The role of this project is to explore suitable architectures to fulfill this essential task including but not limited to the reconfiguration options of the devices from A05 and B01.