ML-Based WCET Estimation on GPU Architectures
Proposing a novel method to estimate the WCET on GPUs using the ML approach by learning the timing model of GPU.
GeNW 14nm Model
14nm Germanium nanowire-based RFET model files. The original paper to be cited is:
J. N. Quijada et al., "Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation," in IEEE Transactions on Nanotechnology, vol. 21, pp. 728-736, 2022, doi: 10.1109/TNANO.2022.3221836.
DeMAS: Library of Approximate Adders
DeMAS is an open-source design methodology for synthesizing and implement approximate adders for any FPGA-based system by considering the underlying resources and architectural differences.
In case of usage of our methodology, please refer to our corresponding DATE-18 paper:
S. Prabakaran et al., "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 917-920. doi: 10.23919/DATE.2018.8342140
Utilizing self-duality through XMG-based logic synthesis for RFETs-based circuit
XMG-based logic synthesis flow for exploiting self-duality for RFETs-based circuits. The code base is already integrated in mockturtle logic synthesis flow .
The benchmarks are available at this github repository
Following papers need to be cited for this work:
S. Rai, H. Riener, G. De Micheli and A. Kumar, "Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies," 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, pp. 354-359, doi: 10.23919/DATE51398.2021.9474112.
S. Rai, A. T. Calvino, H. Riener, G. D. Micheli and A. Kumar, "Utilizing XMG-based Synthesis to Preserve Self-Duality for RFET-Based Circuits," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, doi: 10.1109/TCAD.2022.3184633.
Delta-Compressed Storage Row
Software stack for the paper "dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference"
In case of usage of our methodology, please refer to our corresponding ICCAD-21 paper:
Trommer, Elias, Bernd Waschneck, and Akash Kumar. "dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference." 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). IEEE, 2021.
Physical synthesis flow for RFETs using Cadence encounter flow
Physical synthesis flow for RFETs using different layouts as shown in the following work:
A. Krinke, S. Rai, A. Kumar and J. Lienig, "Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies," 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, pp. 1-9, doi: 10.1109/ICCAD51958.2021.9643439.
https://gitlab.hrz.tu-chemnitz.de/IFTE-EDA/reporo
ABC RFET Mapper: ABC Technology Mapper for Reconfigurable FET based circuits
ABC RFET Mapper is an area-optimized technology mapping which uses the innate reconfigurability, offered by SiNW transistors for efficient circuit designs.
In case of usage of our methodology, please refer to our corresponding DATE-18 paper:
Rai, M. Raitza and A. Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 767-772. doi: 10.23919/DATE.2018.8342110
For queries please contact Prof. Dr. Akash Kumar or Shubham Rai.
RFET Synthesis Design Flow
This is a complete design flow, including both logic and physical synthesis, for circuits based on SiNW RFETs. We propose layouts of logic gates, Liberty and LEF (Library Exchange Format) files to enable further research in the domain of these novel, functionally enhanced transistors.
In case of usage of our methodology, please refer to our corresponding DATE-18 paper:
Rai et al., "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 605-608. doi: 10.23919/DATE.2018.8342080
For queries please contact Prof. Dr. Akash Kumar or Shubham Rai.
Reloc: An Open-Sourced Vivado Workflow for Generating Relocatable, Out-Of-Context End-User Configuration Tiles
The latest repository of the workflow can be downloaded from Here.
Area-Optimized Low-Latency Approximate Multipliers for FPGA-based Hardware Accelerators
We provide a novel approximate multiplier architecture customized towards the FPGA-based fabrics, an efficient design methodology, and an open-source library.
In case of usage of our approximate multipliers, please refer to our corresponding DAC-18 paper:
Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, and Akash Kumar. 2018. Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators. In Proceedings of the 55th Annual Design Automation Conference (DAC '18). ACM, New York, NY, USA, Article 159, 6 pages. DOI: https://doi.org/10.1145/3195970.3195996
For queries please contact Prof. Dr. Akash Kumar or Salim Ullah.
SMApproxLib: Library of FPGA-based Approximate Multipliers
SMApproxLib is an open-source library of approximate multipliers with different bit-widths, output accuracies and performance gains. For each n×n accurate multiplier, we provide three approximate n×n multiplier designs by efficient utilization of LUTs and carry chains.
In case of usage of our approximate multipliers, please refer to our corresponding DAC-18 paper:
Salim Ullah, Sanjeev Sripadraj Murthy, and Akash Kumar. 2018. SMApproxlib: library of FPGA-based approximate multipliers. In Proceedings of the 55th Annual Design Automation Conference (DAC '18). ACM, New York, NY, USA, Article 157, 6 pages. DOI: https://doi.org/10.1145/3195970.3196115
For queries please contact Prof. Dr. Akash Kumar or Salim Ullah.
Open-source Library Download: Main, Sim1, Sim2, Sim3, Sim4, Sim5, Sim6
Accurate and Approximate Softcore Signed Multiplier Architectures
If you use this library in your work, please cite the following paper:
S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman and A. Kumar, "Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures," in IEEE Transactions on Computers, vol. 70, no. 3, pp. 384-392, 1 March 2021, doi: 10.1109/TC.2020.2988404.
For queries please contact Prof. Dr. Akash Kumar or Salim Ullah.
Energy-Efficient Low-Latency FPGA-Optimized Signed Multipliers
If you use this library in your work, please cite the following paper:
S. Ullah, T. D. A. Nguyen and A. Kumar, "Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators," in IEEE Embedded Systems Letters, vol. 13, no. 2, pp. 41-44, June 2021, doi: 10.1109/LES.2020.2995053.
For queries please contact Prof. Dr. Akash Kumar or Salim Ullah.
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators
If you use this library in your work, please cite the following paper:
S. Ullah, S. Rehman, M. Shafique and A. Kumar, "High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 2, pp. 211-224, Feb. 2022, doi: 10.1109/TCAD.2021.3056337.
Hardware Watermarking Tool for Reconfigurable Nanotechnologies
The tool embeds the signature of a designer in his IP design such that all instances of the final IC carry this signature as a watermark. This may prove useful in case the designer wants to contest against fake/counterfeited/overbuilt/pirated copies of his own IP.
More details can be found in our ISVLSI'19 paper:
Rai S, Rupani A, Nath P, Kumar A. "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies". In Proceedings of the ISVLSI'19. IEEE, Miami, FL, USA
In case of any issues, contact: Ansh Rupani (ansh.rupani@tu-dresden.de)
A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications
This is an open-source benchmark developed for LTE applications, in particular the WiBench and Phy-Bench benchmarks.
More details can be found in our paper below. Please cite the paper below when using this library:
Ali Hosseinghorban, Akash Kumar, "A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications", In Electronics, vol. 11, no. 7, 2022. [doi]
AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems
AppAxO provides a generic design methodology for implementing FPGA-based application-specific approximate arithmetic operators. AppAxO's approximate operator modeling technique utilizes lookup tables and carry-chains of FPGAs to implement approximate operators according to the input configurations. It utilizes various machine learning models to evaluate and select configurations satisfying application accuracy and performance constraints. These models are trained using randomly generated configurations. The implementation characterization and statistical error analysis results of these configurations are given below:
- 4x4 Signed Multipliers: Implementation Results, Error Analysis
- 8x8 Signed Multipliers: Implementation Results, Error Analysis
For queries, please contact Dr. Siva Satyendra Sahoo, or Dr. Salim Ullah.
Approximate Soft Multipliers and Dividers
Zahra Ebrahimi along with her co-authors have designed different SISD, SIMD, pipeline, and non-pipelined versions of approximate multipliers and dividers. In case of interest in collaboration and access to the methodology, please contact Zahra. In case of usage of our methodology, please refer to her corresponding paper.