Path H - CRC 912: Highly Adaptive Energy-Efficient Computing (HAEC)


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The DFG Collaborative Research Center (CRC/SFB 912) "Highly Adaptive Energy Efficient Computing(HAEC)" complements this cluster as Path H. HAEC focuses on large-scale, multi-chip computing platforms with disruptive wireless and optical inter-chip interconnects and on hardware/software adaptation methods for a new quality of energy-efficient computing. The understanding generated here can have major impacts on the other System-Oriented Paths and will be challenged in a much wider context. E.g., new devices from the Materials-Inspired Paths could be integrated into HAEC’s computing platform. Therefore, the CRC is scientifically linked to cfAED, even though it is organizationally independent (see CRC 912).

Research Program

Since 2007, the global Internet’s server and network energy consumption and corresponding CO2 pollution exceeds that of worldwide air traffic. Addressing this increasing energy demand and the resulting ecological impact, the goal of the Collaborative Research Center HAEC is to research technologies enabling computing systems with high energy efficiency without compromising on high performance. A straightforward way for improving energy efficiency is to reduce the energy consumption of every individual hardware component in a system.

However, rather than ignoring the characteristics of applications, user communities, and contexts, HAEC strives for a comprehensive application-aware approach. As computational problems require the parallel execution of computational operations with complex and problem-specific intercommunication patterns, HAECs research focuses on highly-adaptive hardware interconnection systems capable of adapting to software needs to achieve a substantially higher level of efficiency than currently possible with fixed connections. In addition, energy efficiency is addressed by novel software-level adaptation schemes focusing on the utility of applications under different environmental conditions. This requires system states of applications and hardware to be monitored and strategies for improving application utility at run-time, taking into account optimizations from these two ends.

On the hardware side, a novel, highly adaptive and energy efficient interconnection architecture will be investigated and shall be demonstrated in the third (i.e., final) 4-year phase of HAEC (2019 – 2023). While state-of-the-art CMOS technology will be considered initially, new insights on efficient communication and computation components from other Paths shall be used to model the energy/ performance tradeoffs when available. On the software side, HAEC’s goal is to provide comprehensive energy-adaptive software technology, which exploits the versatile interconnection architecture for high application utility and that will require many innovations for run-time optimization.

Recent Achievements



All HAEC publications are listed under the following link: